eSPI - Enhanced Serial Peripheral Interface
Introduction
eSPI (Enhanced Serial Peripheral Interface) is born to replace LPC (Low Pin Count) buses. LPC bus is a legacy bus developed to replace ISA (Industry Standard Architecture) bus.
Compared to LPC
Sideband pin communications between chipset and these devices will be converted to in-band messages through the eSPI interfaces as part of the effort to reduce the component pin count and provide a migration path towards elimination of high voltage 3.3V I/O pins.
`Sideband' mentioned above is not the same as `side-bind' in modulation. See this post on Stack Exchange for more information.
Out-Of-Band (OOB) messaging between Out-Of-Band Processor in the chipset and Embedded Controller (EC) or Baseboard Management Controller (BMC) is also tunneled through the new eSPI interface as in-band messages, thus replacing the SMBus interface for this purpose.
Run-time flash sharing between chipset and target devices will be supported over this new interface. The target devices would be able to access the corresponding Flash partition through the Flash Access channel.
Depending on applications, eSPI bus may be active in all the S0-S5 system states. To lower the system power, the eSPI bus frequency and data pins may be a function of the system state.
Essentials
Controller/Target Mode
eSPI operates in controller/target mode, where eSPI dictates the flow of command and data between itself and the eSPI targets by controlling the CS# (Chip Select#) pins for each of the eSPI targets.
Only One CS# at Any Time
At any time, the eSPI controller must ensure that only one of the CS# pins is asserted is asserted based on source decode, thus allowing transactions to flow between the eSPI controller and the corresponding eSPI target associated with the CS# pin.
The eSPI controller is the only component allowed to drive CS# when eSPI Reset# is de-asserted. For an eSPI bus, there is only one eSPI controller and one or more eSPI targets.
Single Controller-Single Target Configuration
In Single Controller-Single Target configuration, the eSPI Reset# could be generated by target (eSPI Reset# driven from target to controller) or controller (driven from controller to target), depending on the configuration.
Single Controller-Multiple Targets Configuration
Multiple SPI and eSPI targets could be connected to the same eSPI bus interface with a multi-drop Single Controller-Multiple Targets configuration. The number of devices that can be supported over a single eSPI bus interface is limited by bus loading and signals trace length.
In this configuration, the clock and data pins are shared by multiple SPI and eSPI targets. Each of the targets has its dedicated CS# and Alert# pins.
In the configuration with multiple targets presents, the eSPI controller may support 2 eSPI Reset# pins, one from target and the other from target. In this case, the controller's eSPI interface will be reset only when all the targets' eSPI interfaces are reset.
eSPI targets such as Flash and TPM are allowed to share the same set of clock and data pins with eSPI targets. These non-eSPI targets are selected using the dedicated CS# pins and they communicate with the controller through SPI specific protocols ran over the eSPI bus.